FPGA-Based Implementation and Software Verification of a 3×3 Convolution Core for Edge AI Systems

Abstract

This study addresses the growing need for lightweight and energy-efficient convolution accelerators in edge artificial intelligence (Edge-AI), where computation is required to occur close to sensors under strict hardware constraints. To support this demand, the paper presents the design and verification of a compact 3×3 convolution core implemented on an FPGA. The research focuses on establishing a reproducible hardware–software coverification workflow that does not rely on physical FPGA boards, which is particularly valuable for academic environments and early-stage prototyping. The convolution module was described in Verilog and functionally validated through behavioral simulation in Xilinx Vivado. In parallel, a Python/NumPy model was developed to replicate the same fixed-point arithmetic, including quantization and ReLU activation. Simulation data exported from Vivado served as the input to the Python verification script. The numerical comparison between the two pipelines demonstrated complete output consistency across all tested pixels, confirming the correctness of the arithmetic pipeline, dataflow control, and activation behavior. The results show that software-driven verification is sufficient to achieve bit-accurate equivalence with the hardware design, significantly reducing development time and improving reproducibility. This workflow provides a practical foundation for future research on scalable FPGAbased convolution accelerators for embedded AI systems.