Low-Power Hardware Implementation and Evaluation of Sparse CNN for MNIST

Abstract

To address the low-power requirements of edge computing, this work takes MNIST classification as a case study and investigates a sparsity-driven lightweight CNN hardware implementation. Under a unified toolchain, we evaluate the gate-level power of the first convolution–pooling block (Conv1) using VCD-based switching-activity analysis. A sparsity sweep is conducted to study the energy–accuracy trade-offs of zero-skipping. On a 500-image evaluation subset, the baseline achieves 98.0% accuracy with 0.236 μW power. Increasing sparsity to 65% reduces Conv1 power to 0.164 μW (30.5% lower) with 96.0% accuracy. When accuracy must remain at the 98.0% baseline level, a 45% sparsity setting yields 0.182 μW power. The comparison between Zero-Skip and Zero-Skip+CE further indicates that the current CE implementation behaves as data gating rather than true clock gating, providing no additional energy benefit.. We provide detailed descriptions of model configuration, sparsity and gating implementation, VCD statistics and power-conversion settings required for reproducible experiments, thereby offering quantitative evidence and engineering guidelines for sparsity selection and energy-efficiency optimization of lightweight CNNs on resource-constrained platforms.