Research on System-level Design Challenges and Solutions for 3D Chiplet Integration

Abstract

With the slowdown of Moore’s Law and the exponential increase in the cost of advanced manufacturing processes, heterogeneous integration technology based on chiplets has become the key path for the continuation of the development of the integrated circuit industry. This technology achieves an optimal balance of system performance, cost and flexibility by densely stacking chip wafers of different process nodes and functions in a threedimensional space. However, from the perspective of system-level design, three-dimensional chiplet integration brings unprecedented challenges in aspects such as architecture partitioning, interconnection standards, physical integration, and design methodologies. This article systematically reviews the core challenges in the design process of three-dimensional chiplet systems, discusses the solutions from system architecture exploration to physical implementation, and looks forward to the future design automation tools and collaborative optimization methods for the chiplet ecosystem.